1. Field of the Invention
The present invention relates to a semiconductor device. In particular, the present invention relates to a semiconductor device whose power consumption is reduced by stopping supply of the power supply voltage to a CPU.
In this specification, a semiconductor device generally means a device which can function by utilizing semiconductor characteristics, and an electrooptic device, a semiconductor circuit, and electronic equipment are all semiconductor devices.
2. Description of the Related Art
Most computers currently used are von Neumann computers employing a stored-program system. The stored-program system is such a system that data necessary for arithmetic processing is stored in a memory device outside a CPU and the data is sequentially read out. To improve performance of arithmetic processing, as well as an increase in an operation speed of the CPU, an increase in speed of loading and storing the data between the CPU and the memory device provided outside the CPU is required.
A cache memory has been used to eliminate a speed difference generated between the CPU and the memory device provided outside the CPU so as to achieve high speed data processing. For example, a high-speed cache memory in which data frequently read out to the CPU is stored and a memory device which has high storage capacity are hierarchically arranged such that a location of the cache memory is close to the CPU and a location of the memory device is away from the CPU. With such a structure, an access speed of the CPU can be increased.
It is also possible to arrange a plurality of cache memories hierarchically. The cache memories at different levels are individually called a primary cache (e.g., low capacity of 16 to 64 KB), a secondary cache (e.g., intermediate capacity of 256 to 512 KB), a tertiary cache (e.g., high capacity of 1 to 8 MB), and the like, in the order of level from closest to the CPU to the farthest from the CPU. As the level where cache memory is arranged is closer to the CPU, the used cache memory has lower capacity and operates at higher speed. The memory devices outside the CPU such as a main memory device and an auxiliary memory device are, in many cases, arranged hierarchically.
The cache memory is incapable of storing all data necessary for arithmetic processing of the CPU. The case where necessary data exists in the cache memory is referred to as “cache hit”, and the case where the necessary data does not exist in the cache memory is referred to as “cache miss”. In the case of a cache miss, it is needed to obtain necessary data from the memory device outside the CPU. Further, when data in the cache memory is updated, the updated data needs to be written back to the memory device outside the CPU. Examples of a method for determining a line in a cache memory which is subjected to rewriting data include a first-in first-out (FIFO) method where the time of storing data is earliest in a cache memory is selected, a least recently used (LRU) method in which a line where the last accessed time is earliest is selected, and the like.
Further, as a control method of update obtained by arithmetic processing of the CPU, a write through method, a write back method, and the like can be given. In the write through method, updated data is stored both in a cache memory and a main memory device at the same time. In other words, even when a line in which the updated data is stored corresponds to a line in which rewriting is performed in the case of cache miss, the updated data is not necessarily written back to the main memory device.
In the write back method, updated data is temporarily stored only in the cache memory. Thus, when a line in which the updated data is stored corresponds to a line in which rewriting is performed in the case of cache miss, the updated data is required to be written back to the main memory device from the cache memory. When the write back method is employed, the frequency of access to the main memory device can be reduced and data processing can be performed at a high rate. Meanwhile, data coherency is not obtained between the cache memory and the main memory device for a certain period of time by employing the write back method. In order to keep data coherency, a dirty bit incorporated in the cache memory can be used.
According to Patent Document 1, write back processing is performed immediately before a CPU enter an idle state, and the idling processing is performed after the write back processing, whereby data coherency is kept and power consumption of the CPU is reduced.
According to Patent Document 2, in the case where the proportion of dirty data in the whole cache data is high, write back processing is performed in such a way that a dirty bit is scanned only when the number of addresses where data is updated exceeds the predetermined number, so that the processing time is reduced.